A GexSe1-x switch-only-memory technology through polarized atomic distribution | Scientific Reports

Scientific Reports volume 14, Article number: 22115 (2024) Cite this article

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Ovonic threshold switching (OTS) materials that are frequently used with a resistor (1S1R) in memory devices have been found to show controllable and reversible memory properties, which could enable new memory architectures. Here, we examine the impact of composition on the polarity-dependent memory properties of GexSe1-x OTS materials and reveal that an increase in Se content results in a higher set voltage threshold (Vth), a lower reset current (IRST), and a higher set energy. Specifically, Ge56Se44 demonstrates two distinct Vth of 5.1 and 3.8 V, which retain after annealing at 85 ℃ for one day. We fabricated Ge56Se44 into 1000 by 1000 cross-point pillar arrays and tested 100 of them. The results demonstrated that these Ge56Se44 devices show similar memory properties with a reset speed of 1 μs, a set speed of 50 ns, and an endurance of over 105 cycles. Interestingly, the Ge56Se44 pillars’ reset and set states could be attributed to polarized atomic distributions. By utilizing GexSe1-x, we demonstrate a true cross-point switch-only-memory technology and provide mechanistic insights for self-selecting OTS materials.

Ovonic threshold switching (OTS) materials, primarily composed of amorphous chalcogenide compounds1, abruptly transition to a high conductance state when a voltage above a certain threshold (Vth) is applied. When coupled with phase-change materials (PCM), OTS enables cross-point memory arrays that are high-density and stackable in three dimensions in contrast to traditional complementary metal–oxide–semiconductor (CMOS) technology2,3. In applications, the high-density cross-point technology constructed with advanced non-volatile materials can achieve a storage class memory4,5 due to its functionality between dynamic random access memory (DRAM) and 3D NAND storage components. Despite the promises, PCM-OTS cross-point arrays, having a thick memory stack consisting of a PCM layer and an OTS layer, are challenging to reach technology nodes of 1z nm where the half-pitch of the active area is 15 nm6. Also, PCM layers need a large reset current to amorphize the PCM memory, leading to high power consumption7 and thermal disturbances on neighboring cells. In response to these challenges, prior studies remove the PCM and adopt specific types of OTS, pioneering a switch-only-memory (SOM) cross-point memory arrays8,9,10. The unique OTS materials for SOM cross-point arrays standing alone can work as a memory element and have distinct polarity-dependent Vth states. Specifically, Vth increases after applying an opposite bias and decreases after a same-direction bias11,12. For example, Taras Ravsher et. al. have shown that 20 nm thick Ge50Se50 exhibits a change in Vth by ~ 2.5 V, and this change is tunable by varying Ge50Se50 thickness and the OTS-electrode interfacial contacts. These findings were attributed to heat-assisted Ge migration that causes Ge to diffuse across a TiN layer upon various programming voltage bias13. Additionally, GeSe can be further improved by doping with copper such that CuGeSe shows memory properties with low program current, short switching time, and good endurance14. OTS showing self-rectifying memory was also observed in other OTS materials, including SiGeAsSe10, SiGeAsTe11,12, and GeAsSe15. However, the polarity-dependent switching behaviors in response to compositional changes are not systematically studied, which hinders the study of OTS exhibiting migration behaviors as well as the elucidation of debating mechanisms.

Here, we report the composition effect on GexSe1-x’s polarity-dependent memory behaviors and demonstrate using Ge56Se44 in a 3D-stackable cross-point array. We screened various GexSe1-x compositions, including Ge61Se39, Ge56Se44, and Ge35Se65, by their threshold voltages using mushroom-type devices. The set (low Vth state, denoted VtS) and reset (high Vth, denoted VtR) states can be reached by positive and negative programming voltages, respectively, where the positive direction is defined to be the direction of the first-fire (FF) process. Our results indicate that VtS increases with Se content, while VtR doesn’t show a clear correlation with Se content. The increase in Se content also leads to a smaller reset current and a larger set energy, indicating a tradeoff when tuning Se content in GexSe1-x. Interestingly, the states of Ge56Se44 are non-volatile as the medians of VtR and VtS don’t change after being annealed at 85 ℃ for one day while the other GexSe1-x have undistinguishable states after annealing, verified using 66 mushroom-type cells for each kind. To demonstrate a memory technology consisting of only Ge56Se44, which has distinct VtR and VtS of 5.1 and 3.8 V, respectively, we further fabricated Ge56Se44 into a high-density 3D-stackable cross-point array containing 1000 wordlines (WL) and 1000 bitlines (BL), totaling one million pillar-type devices. Among all the devices, 100 Ge56Se44 pillar-type devices were operated using a half-V operation scheme2,16. We show that these Ge56Se44 pillar devices maintain VtR of 6.5 V and VtS of 4.0 V with the states’ retention durations of over 1 day at 85 ℃. When repeatedly programmed, the VtR and VtS values remain stable after more than 105 times of operations, showing excellent cycle endurance. These properties suggest that using Ge56Se44 for a SOM cross-point array is comparable to many state-of-the-art one-selector-one-resistor (1S1R) technologies. Furthermore, we found that the polarity-dependent Vth in GexSe1-x is likely related to polarized elemental re-distributions that are affected by external electrical fields through programming voltage sweeps, leading to controllable reset and set states. Our proof-of-concept demonstrations, together with the mechanistic observation, illustrate the great potential for discovering two-state OTS materials for simplified and more efficient 3D cross-point memory technology.

Germanium selenide (GeSe) has gained considerable interest in studying OTS’s memory properties due to its relatively simple binary compositions, environmental friendliness, and high thermal stability1,17,18. To characterize the composition effect on the GeSe’s bipolar switching behaviors, we made three different kinds of GexSe1-x: Ge61Se39 (Ge-rich), Ge56Se44 (middle), and Ge35Se65 (Se-rich) (Fig. 1a). These were deposited as 30-nm thin films using a magnetron sputtering system onto foundry-sourced ring-shaped TiN bottom electrodes (BE), forming mushroom-type memory cells. A 10-nm carbon layer and a 40 nm TiN layer were added atop the GexSe1-x films, collectively serving as the top electrode (TE) for testing purposes (Fig. 1b) (see Methods). The memory cells, composed of BE, GexSe1-x, and TE (Fig. 1c–e) (see Methods), show an FF process when undergoing a direct current (DC) voltage-current sweep19. The completion of the FF process is confirmed when the voltage sweep passes a Vth, indicated by a sudden increase in the current. After FF, a voltage sweep in the opposite polarity programs the cells to a higher Vth state (reset state, VtR), while a sweep in the same polarity programs them to a lower Vth state (set state, VtS). Note that the programming operations were considered complete when the current suddenly increased (Fig. 1f, program completion indicated by gray dashed lines). Once controlled in different states, the cells were read using a voltage sweep in the same direction as the FF operation. The read operation reveals a high VtR in reset states and a low VtS in set states (Fig. 1g). The demonstration of GexSe1-x’s memory properties suggests that conventional memory components such as phase-change material (PCM), resistive random-access memory (RRAM), or magnetoresistive random access memory (MRAM)) (Fig. 1h) can be potentially removed in memory stacks, thus simplifying manufacturing processes. The memory behaviors from simply one layer of GexSe1-x can also facilitate scaling 3D cross-point array memory down to 1z nm technology node8, and potentially be transformable to high-density 3D vertical-NAND type structures13.

GexSe1-x’s polarity-dependent Vth facilitates a new advanced memory architecture. (a) Compositions of GexSe1-x in this study. (b) A ring-shaped BE contacts a material stack composed of a GexSe1-x, a carbon, and a TiN layer. (c–e) Cross-sectional transmission electron microscopy (TEM) images of the mushroom-type memory cells containing (c) Ge61Se39(Ge-rich), (d) Ge56Se44(middle), and (e) Ge35Se65 (Se-rich). Scale bars: 20 nm. (f) After an FF process, a bipolar operation method can program cells to reset and set states. (g) Once the OTS is in reset or set states, read voltages can detect VtR and VtS, respectively. (h) The OTS’s polarity-dependent Vth could reduce the volume of the cross-point memory technology by removing conventional memory units.

To investigate GexSe1-x of various compositions, voltage sweeps of the same polarity were repeatedly applied to our devices containing Ge-rich, middle, or Se-rich GeSe (Fig. 2a,b) (see Methods). Initially, all fresh devices exhibited a high forming Vth observed at the FF process, with Vth increasing from 7.7 to 8.8 V as Se content rose (Fig. 2a). After the FF, subsequent voltage sweeps showed a Vth ranging from 3.5 to 4.2 V, also increasing with Se content (Fig. 2b,c). Note that higher Se content not only raised the Vth but also broadened its distribution from 0.25 to 0.70 V. The threshold switching profiles were further checked for the current at half of their Vth to determine the leakage current (Ioff), which arises across cells that share the activated bitlines or wordlines during cross-point array operations16 and is given by,

GexSe1-x’s memory properties vs. composition changes. (a) OTS materials, GexSe1-x, exhibit high forming voltages in the FF processes. (b) After the FF process, subsequent voltage sweeps observe the OTSs’ Vth values. (c) GexSe1-x’s Vth increases (top) and Ioff decreases (bottom) with higher Se content. (d–e) The GexSe1-x shows VtR and VtS. The inset in (d) illustrates the test sequence: one reverse voltage sweep (I) followed by two forward voltage sweeps (II and III). (f) The top panel indicates that adding Se does not clearly affect VtR but notably increases VtS. The bottom panel demonstrates the ΔVt with increased Se content. The upper and lower edges of the boxes represent the 75 and 25 percentiles of the data.

Our sweeping profiles indicated that Ioff decreased from 6.4 \(\times\) 10-6A to 3.4 \(\times\) 10−8A as Se content increases (Fig. 2c, bottom), which is opposite to the trend of Vthvs. Se content. Beyond GexSe1-x’s conventional OTS properties, we also explored their polarity-dependent memory properties using DC tests in three stages: (I) an opposite DC voltage sweep for resetting cells, (II) a DC voltage sweep for reading out the VtR. This step also sets cells due DC current’s destructive high energy, and (III) a DC voltage sweep for reading out the VtS (Fig. 2d,e). Figure 2d,e show that all GexSe1-x show higher VtR in stage II and lower VtS in stage III. We compared the VtR and VtS among our compositionally different GexSe1-x, and found that the middle GeSe has the highest VtR of 5.1 V, and that VtS increases from 3.6 to 4.2 V with increased Se content. The disproportional changes in the VtR and VtS make the middle GeSe have a larger Vth window (ΔVt = VtR−VtS) of 1.3 V, compared to those of Ge-rich and Se-rich GeSe (Fig. 2f). This correlation between ΔVt and GexSe1-x composition aligns with previous research, which shows a bigger ΔVt from Ge50Se50 compared to Ge60Se4011.

To compare the reset energy, the magnitude of the reset current was varied before VtR was read (Fig. 3a and see Methods). Figure 3b summarizes GexSe1-x’s different VtR reached by reset currents ranging from 2 to 100 μA and indicates that the reset current required for a ΔVt of more than 1.0 V decreases with increasing Se content (Fig. 3c). The set programming energy was investigated by using 50 ns box set pulses of various magnitudes after a 100μA reset current (Fig. 3d and see Methods). The VtS vs. set current shows that the set pulse current applied to lower the VtS for a ΔVt of more than 1.0 V is 323 μA and 393 μA for Ge-rich and middle Ge56Se44, respectively (Fig. 3e,f). The Se-rich was not able to set using 50 ns pulses (Fig. S1), and it requires ~ 171 μA 40 μs pulses (Fig. 3f, right panel), potentially due to large bonding energy in Se-Se bonds (44.00 kcal mol−1), compared to that in Ge–Ge bonds (37.60 kcal mol−1)20. To check the retention performance of the reset and set states, 33 reset cells and 33 set cells were annealed at 85 oC for one day (see Methods). Post-annealing we found that only the middle GeSe retains its VtR and VtS and has a roughly unchanged ΔVt of 1.2 V, exhibiting a better retention property compared to the Ge-rich and the Se-rich GeSe (Fig. 3g,h).

GexSe1-x’s programming current and retention properties vs. composition changes. Reset current tests (a) show that GexSe1-x’s VtR rises with reset current up to 100 μA (b–c). A 50 ns-pulse is employed (d) to program Ge-rich and middle GeSe to set states. A 40 μs-pulse is used for Se-rich GeSe. (e,f) The VtS vs. set current profiles show that GexSe1-x’s VtS decreases with higher set currents up to 500μA. (g–h) The GexSe1-x VtR and VtS before and after being annealed at 85 °C for one day. The upper and lower edges of the boxes represent the 75 and 25 percentiles of the data.

The middle GeSe, Ge56Se44, was selected to demonstrate in cross-point arrays because of its larger ΔVt memory window compared to those of our other GexSe1-x. Ge56Se44 were fabricated as pillar-type devices on a foundry-sourced wafer that uses 130 nm-CMOS technology. One million Ge56Se44 pillars were fabricated, each flanked by carbon layers and positioned at the intersections of 1000 WL and 1000 BL metal lines (Fig. 4a–c, see Methods). 100 Ge56Se44 cross-point devices were selected for electrical testing, where 0 V is supplied to each device’s corresponding WL, and a predetermined voltage is applied to the BL. The WL and BL of unselected devices are maintained at 3 V (see Methods). This selection method allows for reset, set, and read operations for individual devices. We found that Ge56Se44 devices can exhibit a VtR and VtS of 6.5 and 4.0 V, respectively, and the majority of the working cells have ΔVt of ~ 1 V (Fig. 4d,e). When we use write pulses of various lengths, we found that a 1 μs-pulse leads to a VtR of 6.25 V (Fig. S2). Our tester’s shortest pulse of 50 ns leads to a VtS of 4.75 V (Fig. S3). The data retention characteristic was assessed by annealing the devices at 85 oC for one day, resulting in changes in the median values of VtR and VtS by 0.5 and 0 V, respectively (Fig. 4f and see Methods). The endurance of the device was also tested through repeated write operations (see Methods), and the results demonstrated that Ge56Se44 devices can maintain a ΔVth of ~ 1.5 V for over 105 cycles (Fig. 4g). Overall, our Ge56Se44 cross-point array prototype not only demonstrates a two-state memory characteristic but also exhibits many features that are comparable or superior to other cross-point array memory technologies (Table 1). For example, traditional 3D cross-point memory (1S1R) technologies using an OTS as a selector and a PCM as a memory cell require over 400 μA to reset due to amorphization of PCM and typically take hundreds of nanoseconds to set due to crystallization of PCM, whereas our SOM cross-point arrays could potentially operate more efficiently. For other 1S1R structures using OTS as a selector with RRAM memory cells, they may require a long latency of micro-second level set time21. SOM cross-point arrays have shown low programming energy and simplified manufacturing processes that are crucial for new emerging technologies such as compute express link (CXL)8, but have yet to outperform existing memory technology in all properties. Despite the promising results of our proof-of-concept demonstration, it should be noted that further innovations in SOM materials are required to surpass other key metrics in memory technologies.

A prototype of the Ge56Se44-only cross-point array. (a) The Ge56Se44-only cross-point array selects a Ge56Se44 pillar by supplying a predetermined voltage through its BL while controlling a voltage of 0 V on its WL. Inset: A zoom-in illustration of a single Ge56Se44 pillar. (b–c) The top view (b) and cross-sectional (c) TEM images of our Ge56Se44-only cross-point array prototype. Scale bar in (b): 1 μm and in (c): 200 nm. (d) The Ge56Se44 pillars in the array show VtR and VtS. (e) The ratio histogram of the working cells’ ΔVt. (f) The VtR and VtS change after annealing at 85 oC for one day. (g) Changes in VtR and VtS observed over 105 cycles of reset and set states. The upper and lower edges of the boxes represent the 75 and 25 percentiles of the data.

Analyzing the cross-sections of the device in cross-point arrays, we observed that the polarity-dependent Vth of Ge56Se44 may be related to the distribution of Ge and Se atoms (see Methods). Initially, in the absence of any programming operations, the Ge56Se44 device exhibits a uniform distribution of Ge and Se from the bottom electrode (BE) to the top electrode (TE) (Fig. 5a–c). However, after a reset programming operation, signals of Ge and Se become more enhanced near the TE and BE, respectively (Fig. 5d–f). Conversely, when a set programming operation is conducted, the distribution is reversed: the Ge signal intensifies near the BE, and the Se signal strengthens near the TE (Fig. 5g–i). To quantify the skewed distribution of GexSe1-x across the electrodes, we scaled the Se signals using Eq. 1 to have Ge and Se signals’ area integrals proportional to their atomic ratio. Subsequently, we calculated the Ge and Se ratios across the GeSe layer by Eqs. (2, 3):

where EGe and ESe are the Ge and Se’s EDX signals, and A is the cross-sectional area of the GeSe layer. α is a scaling factor that accounts for the differences in the detector’s sensitivities toward Ge and Se and enables quantitative comparisons across different elements. xGe and xSe are the atomic ratios of Ge and Se, respectively. We discovered that in the reset states, the GexSe1-x composition near the BE resembles that of Se-rich GeSe. Moving away from the TE by approximately 10 nm, the composition transitions to middle GeSe, and within a 10 nm range close to the TE, the Ge content increases by 20%, indicating a highly Ge-rich composition (Fig. 5j). At the set state, the trend is reversed, presenting highly Se-rich GeSe at the TE and Ge-rich GeSe at the BE (Fig. 5k). It is very likely that the Vth is heavily influenced by the GexSe1-x composition nearest to the source of the external electric field during a read operation. In our case, the electric field primarily affects the GexSex-1 near the BE, prompting electron flows through the compositionally varying GexSe1-x. In the reset state, Se-rich GeSe is located closer to the BE. This atomic distribution enables a high Vth, adhering well to our observation of Se-rich GeSe showing a higher Vth (Fig. 2c). Se-rich GeSe’s high energy barrier can also be explained by the reduced number of charge traps24 and the bandgap widening seen in Se-doped GeSbTe alloys25. In the set states, Ge-rich GeSe is closer to the BE. This atomic distribution enables a lower Vth, similar to our results of the Ge-rich GeSe (Fig. 2c). This behavior could potentially be explained by the Ge–Ge bonds formed when Ge is in excess. The Ge–Ge bonding creates tail states in the conduction band and facilitates conduction even at low electric fields26,27. We note that the middle GeSe’s better performance is likely attributed to an overall intermediate composition, where the reset and set states are not solely governed by either Se’s or the Ge’s effects, but governed by two distinct atomic environments28. The band structure of GexSe1-x across a polarized distribution is needed to elucidate the origin of elemental-distribution-governing memory properties. This hypothesis suggests that high-performance OTS-memory materials benefit from significant polarity-dependent elemental gradients.

The Ge and Se distribution in the Ge56Se44 pillars. (a–c) Before programming, cross-sectional TEM (a) and elemental mapping images (b) of a Ge56Se44 pillar show a uniform distribution of Ge and Se across the TE and BE (c). (d–f) In the reset state, cross-sectional TEM (d) and elemental mapping images (e) reveal Ge migration towards the TE and Se migration towards the BE (f). (g–i) In the set state, cross-sectional TEM (g) and elemental mapping images (h) display Ge moving towards the BE and Se toward the TE (i). The x-axes in c, f, and i are in the directions from the BE to the TE. Scale bars: 100 nm. Note that the Se signal is scaled by α in panels c, f, and i. (j–k) The distribution of Ge content in the reset (j) and set states (k).

In conclusion, our study demonstrates that GexSe1-x exhibits polarity-dependent memory properties, characterized by a VtR of 5.1 V and a VtS of 3.8 V. These properties, together with the demonstrated endurance of over 105 cycles and a retention capability after annealing at 85 oC for one day in Ge56Se44 pillar devices, highlight the substantial potential of OTS materials for SOM 3D cross-point memory technologies. The new generation of 3D cross-point memory technology using SOM approach could simplify integration processes and lead to cheaper cost per bit, enabling high-density compute express link (CXL) technology8. The distribution of Ge and Se atoms in reset and set states provides insight into the fundamental mechanisms underlying the polarity-dependent Vth in OTS materials. The changes in Vth are likely due to the compositionally diverse GexSe1-x across the electric field, where electrons move at varying field strengths. We anticipate that, as observed in Ge56Se44, OTS compositions capable of reversibly forming polarized distributions will be crucial for the rational design of OTS materials tailored for SOM technologies.

We envision that this emerging SOM based 3D cross-point array technology could offer numerous advantages over traditional 1S1R 3D cross-point technologies even with the capability to extend to vertical 3D NAND-type cross-point technology9,29. Most importantly, these improvements could directly lower the cost per bit of memory. We expect that our proof-of-concept testing with GexSe1-x and the demonstration of switch-only cross-point arrays will not only inspire further innovations in the OTS memory materials but also advance the technological evolution of SOM for next generation of 3D cross-point memory technology.

Ge61Se39 were made by co-sputtering Ge and Ge57Se43, Ge56Se43 were made by sputtering Ge57Se43, and the Ge35Se65 was made by sputtering Ge33Se66. All sputtering processes were run using a magnetron sputtering system (AJA International, Inc.) equipped with a radio-frequency (RF) power supply. To quickly verify new SOM materials characteristics, short turnaround time mushroom-type structure lift-off devices with 100-nm diameter ring-shaped TiN BE were used. 30 nm of these GeSe were deposited onto these foundry-sourced wafers that have controlling transistors allowing individual device characterization. Subsequently, a 10-nm C layer was deposited using direct current (DC) power on a C target, and a 40-nm tungsten film was deposited using DC power, collectively serving as the TE. Note that the wafer’s transistor control pads are covered by photoresists. To lift off the photoresist and expose the transistor control pads, the wafers were bathed in acetone at room temperature with a stir bar spinning and rinsed using isopropyl alcohol (IPA), which complete the full stacking PVD deposited memory cells.

We used a cascade wafer prober (Summit 12000 A, Cascade Microtech) to probe the wafer’s transistor control pads and an address switching matrix (707A, KEITHLEY) to access each transistor. To perform FF, set, VtR read, and VtS read operations, a precision semiconductor parameter analyzer (4156C, Agilent) supplies drain voltage sweeps from 0 to 9 V, a gate voltage of 3 V, a source voltage of 0 V, and a base voltage of 0 V while measuring the drain current. To perform the reset operation, the parameter analyzer supplies source voltage sweeps from 0 to 9 V, a gate voltage of 8.0 V, a drain voltage of 0 V, and a base voltage of 0 V while measuring the source current. The maximum drain and source current was set to 100 μA, limited by a compliance setting. For the pulse set operation, a pulse-/pattern generator (81110A, Agilent) applies a drain voltage and a gate voltage pulse, and an oscilloscope captures the drain current. The retention capabilities of GexSe1-x are determined by comparing the VtR and VtS before and after an 85 ℃ annealing for one day. The annealing was done in an oven that is set at 85 ℃ and purged with nitrogen. The endurance test was done by repeatedly writing the GexSe1-x to its reset and set states using AC pulses. The VtR and VtS are read after the first, 10th, 100th, 1,000th, 10,000th, and 100,000th cycle.

Starting with a foundry-sourced wafer that has 130 nm-CMOS technology with copper WLs, we fabricated TiN BEs using a standardized via fabrication process30. On the BEs are 10 nm C, 30 nm Ge56Se44, and 15 nm C layers that were deposited at room temperature using magnetron sputtering systems. A 1 nm Ti/75 nm TiN layer was deposited, serving as the TE. Subsequently, the whole stack above the BEs was patterned to pillars using reactive ion etching (RIE) processes. The pillars were capped with dielectric materials, and then a chemical mechanical polishing (CMP) process flattened and exposed the TiN TEs. To connect the pillars’ TEs, a uniform 40 nm metal layer was deposited, and a metal RIE process patterned the layer to form the BLs.

Before the TEM (Titan TEM/STEM, Thermo Fisher Scientific) and energy-dispersive X-ray spectroscopy (EDX) analyses, the GeSe cells that were at non-programmed, reset, and set states were prepared. Those cells were made into slices following a standard lift-out process using a scanning electron microscope—focused ion beam (SEM-FIB) dual beam system (Helios 5 FX, Thermo Fisher Scientific). The elemental mapping uses an EDX detector during the TEM imaging.

The datasets used in this study are available from the corresponding author upon reasonable request.

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The authors would like to thank Holt Bui for measuring OTS’s compositions using Rutherford backscattering spectrometry (RBS).

IBM/Macronix PCRAM Joint Project, Yorktown Heights, NY, 10598, USA

Zhi-Lun Liu, Alexander Grun, Wei-Chih Chien, Asit Ray, Erh-Kun Lai, Matt BrightSky, Hsiang-Lan Lung & Huai-Yu Cheng

Macronix International Co., Ltd., Hsinchu, Taiwan

Wei-Chih Chien, Erh-Kun Lai, I-Ting Kuo, Hsiang-Lan Lung & Huai-Yu Cheng

Macronix America Inc., Milpitas, CA, 95035, USA

Zhi-Lun Liu, Alexander Grun, Wei-Chih Chien, Erh-Kun Lai, Hsiang-Lan Lung & Huai-Yu Cheng

IBM Research, Yorktown Heights, NY, 10598, USA

Asit Ray, Lynne Gignac, Christian Lavoie & Matt BrightSky

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Z.-L.L. and H.-Y.C. conceived this study. Z.-L.L. and A.G. fabricated and tested the mushroom-type devices containing GexSe1-x. A.R. and E.-K.L. fabricated Ge56Se44 cross-point arrays. W.-C.C performed Ge56Se44 cross-point array electrical tests. C.L., L.G., and I.-T.K. performed TEM analyses. All authors contributed to data analysis and discussed the results. Z.-L.L. wrote the paper. H.-Y.C., M.B., and H.-L.L. supervised this project.

Correspondence to Huai-Yu Cheng.

The authors declare no competing interests.

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Liu, ZL., Grun, A., Chien, WC. et al. A GexSe1-x switch-only-memory technology through polarized atomic distribution. Sci Rep 14, 22115 (2024). https://doi.org/10.1038/s41598-024-73131-2

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Received: 02 July 2024

Accepted: 13 September 2024

Published: 27 September 2024

DOI: https://doi.org/10.1038/s41598-024-73131-2

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